CPHA=0, SCKDEN=0, SLNDEN=0, LSBF=0, SSLA=000, CPOL=0, BRDV=00, SSLKP=0, SPNDEN=0
SPI Command Register
| CPHA | RSPCK Phase 0 (0): Data is sampled at an odd edge and changes at an even edge. 1 (1): Data changes at an odd edge and is sampled at an even edge. |
| CPOL | RSPCK Polarity 0 (0): RSPCK in idle state is 0. 1 (1): RSPCK in idle state is 1. |
| BRDV | Bit Rate Division 0 (00): The base bit rate is selected. 1 (01): Two-divided base bit rate is selected. 2 (10): Four-divided base bit rate is selected. 3 (11): Eight-divided base bit rate is selected. |
| SSLKP | SSL Signal Level Hold 0 (0): All SSL signals are negated at the end of transfer. 1 (1): SSL signal level is held after the transfer ends until the next access starts. |
| LSBF | SPI LSB First 0 (0): MSB first 1 (1): LSB first |
| SPNDEN | SPI Next-Access Delay Enable 0 (0): Next-access delay is 1RSPCK + 5TCLK 1 (1): Next-access delay is the set value of the SPI next-access delay register (SPDECR.SPNDL). |
| SLNDEN | SSL Negation Delay Setting Enable 0 (0): [Master] SSL negation delay is 1RSPCK. [Slave in the TI-SSP] SSL negation delay is 1TCLK 1 (1): SSL negation delay is the set value of the slave select negation delay register (SPDECR.SLNDL). |
| SCKDEN | RSPCK Delay Setting Enable 0 (0): RSPCK delay is 1 RSPCK. 1 (1): RSPCK delay is the set value of the RSPCK delay register (SPDECR.SCKDL). |
| SPB | SPI Data Length |
| SSLA | SSL Signal Assertion 0 (Others): Setting prohibited 0 (000): SSL0 1 (001): SSL1 2 (010): SSL2 3 (011): SSL3 |